Zedboard_Multi_Module_IP

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ZedBoard shift Light by Mulit IP


1、Create First Project

Project Name : “divider_module” -> Create SystemVerilg : divider.sv -> Create constraints : divider_ooc.xdc -> Choose “Boards / ZedBoard Zynq Evaluation and Development Kit” -> Finish

Edit divider.sv

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module divider(
  input clk,
  input rst,
  output logic clk_div
);

  logic [25:0] cnt;

  always_ff @(posedge clk or posedge rst) begin
    if (rst) begin
      cnt <= 26'd0;
      clk_div <= 'b0;
    end
    else begin

      if (cnt == 62500000) cnt <= 26'd0;
      else cnt <= cnt + 1;

      if (cnt < 31250000) clk_div <= 'b0;
      else clk_div <= 'b1;
    end
  end

endmodule

Edit divider_ooc.xdc

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create_clock -period 8.000 -name sys_clk_pin -waveform {0.000 4.000} -add [get_ports clk]
create_generated_clock -divide_by 125000000 -source [get_ports clk] [get_ports clk_div];

Out-of-Context XDC files setting

Package the frequency divider IP

Close divider_module Project


2、Create Second Project

Project Name : “blinky_module” -> Create SystemVerilg : blinky.sv -> Create constraints : blinky.xdc , blinky_ooc.xdc -> Choose “Boards / ZedBoard Zynq Evaluation and Development Kit” -> Finish

Edit blinky.sv

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module blinky(
  input clk,
  input rst,
  input [1:0] sw,
  output logic [3:0] led
);

  logic dirct;


  always_ff @(posedge clk or posedge rst) begin
    if (rst) begin
      led <= 4'b0000;
    end
    else begin
      if (!dirct) begin
        if (led == 0) led <= 4'b0001;
        else led <= led << 1;
      end
      else begin
        if (led == 0) led <= 4'b1000;
        else led <= led >> 1;
      end
    end
  end


  always_comb begin
    case (sw)
      2'b01: dirct = 1'b0;
      2'b10: dirct = 1'b1;
      default: dirct = 1'b0;
    endcase
  end

endmodule

Edit blinky.xdc

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set_input_delay 0.1 [get_ports {sw[1] sw[0] rst}];
set_output_delay 0.1 [get_ports {led[3] led[2] led[1] led[0]}];
set_max_delay 0.1 -from [get_ports {sw[1] sw[0] rst}] -to [get_ports {led[3] led[2] led[1] led[0]}];

Edit blinky_ooc.xdc

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create_clock -period 8.000 -name sys_clk_pin -waveform {0.000 4.000} -add [get_ports clk]

Following is like the last project : Out-of-Context XDC files setting -> Create and Package New IP -> Package your current project -> edit Ports and Interfaces -> Package IP

Close blinky_module Project


3、Create top Project

Project Name : “top” -> Next -> Choose “Boards / ZedBoard Zynq Evaluation and Development Kit” -> Finish

Include divide IP, Path :”Your path”\divider_module\divider_module.srcs

Include blinky IP, Path :”Your path”\blinky_module\blinky_module.srcs

Create Block Design

Create Port and connect module

Run Synthesis -> Run Implementation -> Open Implementation

top.xdc

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set_property PACKAGE_PIN U14 [get_ports {led[3]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]
set_property PACKAGE_PIN W22 [get_ports {led[1]}]
set_property PACKAGE_PIN V22 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports clk]
set_property IOSTANDARD LVCMOS18 [get_ports {sw[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {sw[0]}]
set_property PACKAGE_PIN F22 [get_ports {sw[0]}]
set_property PACKAGE_PIN G22 [get_ports {sw[1]}]
set_property PACKAGE_PIN Y9 [get_ports clk]
set_property IOSTANDARD LVCMOS18 [get_ports rst]
set_property PACKAGE_PIN M15 [get_ports rst]

Create HDL Wrapper

Run Synthesis -> Run Implementation -> Generate Bitstream -> Open Hardware Manager -> Auto Connect -> Program


Reference

NCKU FPGA_Design